// LFSR 模块，用于生成 M 序列
module lfsr #(
    parameter K = 4,  // LFSR 的长度
    parameter TAPS = 4'b1001  // 反馈抽头系数
) (
    input wire clk,
    input wire rst_n,
    output reg [K-1:0] state,
    output wire m_sequence
);
    reg feedback;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state <= {K{1'b1}}; // 初始化为全 1
        end else begin
            feedback = ^(state & TAPS);
            state <= {state[K-2:0], feedback};
        end
    end

    assign m_sequence = state[K-1];

endmodule    